/* 功能定义：一段式FSM产生连续二进制序列检测
*/
module Fre_Check(Clk,Rst_n,Din,Dout);
input Clk;
input Rst_n;
input Din;
output reg Dout;
reg [3:0] Next_State;
parameter
IDLE = 0,
st0 = 1,
st1 = 2,
st2 = 3,
st3 = 4,
st4 = 5,
st5 = 6,
st6 = 7,
st7 = 8;
always @(posedge Clk or negedge Rst_n)
if(!Rst_n)begin
Next_State = IDLE;
Dout = 1'b0;
end
else begin
case(Next_State)
IDLE: if(Din) begin Next_State = st0;Dout = 1'b0;end
else begin Next_State = IDLE;Dout = 1'b0;end
st0: if(Din) begin Next_State = st1;Dout = 1'b0;end
else begin Next_State = IDLE;Dout = 1'b0;end
st1: if(!Din)begin Next_State = st2;Dout = 1'b0;end
else begin Next_State = st0;Dout = 1'b0;end
st2: if(!Din)begin Next_State = st3;Dout = 1'b0;end
else begin Next_State = IDLE;Dout = 1'b0;end
st3: if(Din) begin Next_State = st4;Dout = 1'b0;end
else begin Next_State = IDLE;Dout = 1'b0;end
st4: if(Din) begin Next_State = st5;Dout = 1'b0;end
else begin Next_State = IDLE;Dout = 1'b0;end
st5: if(!Din)begin Next_State = st6;Dout = 1'b0;end
else begin Next_State = st1;Dout = 1'b0;end
st6: if(Din) begin Next_State = st7;Dout = 1'b0;end
else begin Next_State = st1;Dout = 1'b0;end
st7: begin Next_State = IDLE;Dout = 1'b1;end
default:begin Next_State = IDLE;Dout = 1'b0;end
endcase
end
endmodule
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