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学习xilinx FPGA，自己学习编写一个计数器的verilog HDL的程序，在仿真激励上编写始终不过，总报语法错误，郁闷啊。下面贴出这个程序，以便自己今后记住：
module cnt_4bit(q, clear,clock
);
input clear,clock;
output[3:0] q;
reg[3:0] q;
always @(posedge clear or negedge clock)
begin
if(clear)
q = 4'd0;
else
q = (q + 1) % 16;
end
endmodule
test bench的激励程序：
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:00:26 11/19/2015
// Design Name: cnt_4bit
// Module Name: E:/xilinx/study/project2/mux2_1/tb_cnt_4.v
// Project Name: mux2_1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cnt_4bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_cnt_4;
// Inputs
reg clear;
reg clock;
// Outputs
wire [3:0] q;
// Instantiate the Unit Under Test (UUT)
cnt_4bit uut (
.q(q),
.clear(clear),
.clock(clock)
);
initial begin
// Initialize Inputs
clear = 0;
clock = 0;
// Wait 100 ns for global reset to finish
//#100;
// Add stimulus here
//clock = 1'b0;
always
#5 clock = ~clock;
begin
clear = 1'b1;
#15 clear = 1'b0;
#180 clear = 1'b1;
#10 clear = 1'b0;
#20 $finish;
end
end
initial
$monitor($time,"output q = %d",q);
endmodule
书写完成就报错误：
ERROR:HDLCompiler:806 - "E:/xilinx/study/project2/mux2_1/tb_cnt_4.v" Line 53: Syntax error near "always".
找了半天没找出错误原因。郁闷！！
苦解：不知什么原因，配对begin....end修订激励程序
module tb_cnt;
// Inputs
reg clear;
reg clock;
// Outputs
wire [3:0] q;
// Instantiate the Unit Under Test (UUT)
cnt_4 uut (
.q(q),
.clear(clear),
.clock(clock)
);
initial begin
// Initialize Inputs
clear = 0;
clock = 0;
// Wait 100 ns for global reset to finish
//#100;
// Add stimulus here
//clock = 1'b0;
end
always #5 clock = ~clock;
initial begin
clear = 1'b0;
#15 clear = 1'b0;
#180 clear = 1'b1;
#10 clear = 1'b0;
#20 $finish;
end
initial
$monitor($time,"output q = %d",q);
endmodule
终于迎来了光明，第一例程序终于活了。仿真结果如图。
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